The invention is concerned with an input signal level converter for an MOS digital circuit which is constructed in n-channel MOS technology together with the MOS digital circuit. The signal input charged by a TTL signal serves for the control of a first and of a second MOS field effect transistor. The source terminal of the first MOS field effect transistor lies at the supply terminal carrying the reference potential and its drain terminal lies at the source terminal of the second MOS field effect transistor on the one hand and is connected, on the other hand, via the source-drain segment of a third MOS field effect transistor to the supply terminal supplying the supply potential. The drain terminal of the second MOS field effect transistor forms the signal output of the converter and is connected to the supply potential via the parallel connection of a fourth MOS field effect transistor and the series connection of a bootstrap capacitor and a fifth MOS field effect transistor wired as a resistor. The signal output is directly connected to the signal input of the MOS digital circuit which employs the same reference potential and the same supply potential as the signal level converter.
A known circuit for an input signal level converter is illustrated in FIG. 1. In order to be able to describe the objective leading to the present invention more precisely, the circuit according to FIG. 1 functioning as a Schmitt trigger will be described. It is preferably constructed with an n-channel MOS field effect transistor of the self-inhibiting type.
The signal input E of the known circuit is present at the gate of a first MOS field effect transistor t1 and at the gate of a second MOS field effect transistor t2 via a dropping resistor R. The source terminal of the first transistor t1 is connected to the supply terminal carrying the reference potential V.sub.ss and its drain is connected to the source terminal of the second MOS field effect transistor t2 as well as at the source terminal of a third MOS field effect transistor t3. The drain terminal of the second MOS field effect transistor t2 is connected to the gate of the third MOS transistor t3 on the one hand and--together with the source terminal of the fourth MOS field effect transistor t4--forms the signal output A of the level converter on the other hand. The fourth MOS field effect transistor t4 has its drain at the supply terminal carrying the supply potential V.sub.DD and has its gate lying at the source terminal of a fifth MOS field effect transistor t5 whose drain and whose gate are connected to the terminal for the supply potential V.sub.DD. The connection between the gate and the source of the fourth transistor t4 is realized by a MOS capacitor C which leads to a bootstrap effect. Finally, the signal output A can also be connected to the post for the reference potential V.sub.ss by means of a load capacitor (parasitic under given conditions) CL which, for example, is given by the MOS digital circuit to be controlled. This is likewise charged by the supply potential V.sub.DD and the reference potential V.sub.ss and has its signal input lying at the signal output A of the level converter. The level converter is preferably monolithically combined with the digital MOS circuit (not shown in the Figure). The drain of the third transistor t3 lies at the potential V.sub.DD.
The following can now be noted in conjunction with the known circuit according to FIG. 1. The circuit serves the purpose of being able to use the data supplied by a bipolar TTL logic for charging an MOS digital circuit, for example a dynamic RAM memory. The standard level of the digital signals supplied from the output of a TTL logic lies at a minimum of 2.4 V in the high condition and at a maximum of 0.8 V in the low condition. For an n-channel MOS circuit, the level U.sub.Amax =V.sub.DD and the level U.sub.Amin is about equal to 0 V. The level conversion should be executed with the lowest possible dissipation and with the lowest possible delay.
The level converter circuit has low input capacitance and a low output voltage (referred to as V.sub.ss).
The circuit illustrated in FIG. 1, then, guarantees that the output voltage becomes U.sub.A =V.sub.DD even given a signal input voltage U.sub.E =0.8 V and U.sub.T &lt;0.8 V. Due to the bootstrap capacitor C, the gate of the transistor t4 connected to the signal output A to the supply potential V.sub.DD receives a sufficiently high voltage in order to hold the transistor t4 in the startup region during the entire switchover operation. The output voltage U.sub.A of the converter can thus obtain the value V.sub.DD. Furthermore, the dynamic reloading operation of the load capacitor CL is favorably influenced because the internal resistance of an MOS transistor, of course, is lower in the startup region than in the saturation region.
The pre-charging of the bootstrap capacitor C to the voltage value U.sub.C =V.sub.DD -U.sub.T (U.sub.T =threshold voltage of the MOS field effect transistor) leads, however, to two disadvantageous phenomena:
(a) Since the gate voltage of the MOS transistor t4 is already relatively high (U.sub.G =V.sub.DD -U.sub.T) in the idle condition (U.sub.E =high) and, on the other hand, the output voltage U.sub.A is nonetheless supposed to be as low as possible, an unfavorable proportion of t4 to t2 and t1 of about 1 to 10-20 results for U.sub.A &lt;0.5 V (rule of thumb: t4 with 1 W/L=&gt;t2/t1 with 10-20 W/L).
(b) Since the dynamic behavior given fast edges of input signals U.sub.E is defined by the transistor t4 and by the load capacitor CL, a relatively high quiescent current which is essentially defined by the transistor t4 belongs to a given edge slope t.sub.r of the output voltage and to a given load capacitor CL. There is also an input capacitance defined by the gate capacitance of t1 and t2. In conjunction with a dropping resistor R conditioned, for example, by an input protection structure of the monolithically integrated circuit, this can effect a noticeable delay of the output signal U.sub.A relative to the initiating input signal U.sub.E.